When an inexpensive, large-capacity DRAM is utilized as the main memory of a microcomputer, it is possible to design an internal bus within a CPU chip at a speed higher than that of an external bus that connects to the DRAM. By raising the clock of the CPU internal bus and designing the CPU circuit, the processing capability of the computer system equipped with such a CPU can be improved. In such a computer system, a cache memory is generally interposed between the internal bus and the external bus in order that memory access from the CPU to the external bus will be performed efficiently.
Since such a cache memory resides between the internal bus of the CPU and the external bus, the cache memory is transparent as viewed from the CPU side. However, if an external memory has been read or written via the external bus, as in DMA, there will be instances where the data in the cache memory and the data in the main memory do not coincide. Methods used to avoid this problem include a method of clearing or flushing (writing cache content back to memory) the cache memory with respect to the memory area that undergoes the DMA transfer before and after the DMA transfer is performed via the external bus, and a method whereby the memory area that undergoes the DMA transfer is made uncacheable.
An operating system currently in wide use is an embedded operating system having an API (Application Program Interface) that dynamically allocates the memory area used in a DMA transfer. Such an operating system acquires the memory area from a memory manager and controls a cache controller so that the memory area acquired can be made uncacheable. In general, a cache controller has a memory area setting function and is capable of designating a cacheable area and an uncacheable area for each memory area. However, there is a limitation upon the number of registers in the cache controller for the purpose of designating such memory areas. In addition, the larger the number of areas that can be designated, the greater the redundancy of the circuitry. This means that such memory areas cannot be designated without limit.
On the other hand, with application software that utilizes DMA, an improvement in efficiency of DMA transfer is contemplated by providing a plurality of buffers with regard to one DMA channel. For example, during DMA transfer to the first buffer, preparations for a DMA transfer to the second buffer and post-processing are executed.
In view of these circumstances, it is preferred that the number of designatable uncacheable areas be several times larger than the number of channels that can be utilized in such a system. If the number of channels in DMA is large, however, there is an increase in the number of registers for such area control and, hence, there is a great increase in the scale of the circuitry.
Another method is to prepare a large uncacheable area in advance and allocate the uncacheable area by a memory manager that manages this area. In such case, it is necessary that the area of the uncacheable memory is decided statically. This lowers the utilization efficiency of the memory overall.